Cypress Semiconductor /psoc63 /SRSS /PWR_BUCK_CTL

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Interpret as PWR_BUCK_CTL

Description

Buck Control Register

Fields

BUCK_OUT1_SEL	Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V
BUCK_EN	Master enable for buck converter. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.
BUCK_OUT1_EN	Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The SAS specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1.

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